1. Technical Field
The present disclosure relates to integrated circuits, and more particularly, to triggering a component for masking a signal from a clock source.
2. Related Art
Most integrated circuits communicate data between components by way of one or more data busses. A data bus provides a channel for communicating data between two or more components within a single integrated circuit, or between components (or devices) on two or more integrated circuits. A bidirectional data bus can communicate data in either direction between two components so that the components use the same bus for data flow in both directions. Typically, a memory controller manages the flow of data between the components. For example, a memory controller may send command signals to the components to indicate that, for a specified time interval, a first component is to send data to the bus and a second component is to receive the data from the bus.
A circuit or system that implements a bidirectional data bus may utilize more than one clock domain. For example, the memory controller, the first component, and the second component discussed above may each have a clock driver to generate clock signals for component activity, such as data transfer. Typically, the timing of data latching/communication over a bidirectional data bus, for both the sending and receiving component, is controlled by the clock driver associated with the component that is sending the data. In other words, the component that is receiving the data also receives the clock signal that is generated by the clock driver of the component that is sending the data. The components may share a clock line, such as a bidirectional clock line or clock bus, for communicating their clock signals to one another.
Typically, when the clock line is not being driven (i.e., carrying a clock signal) by either clock driver, it is latent and in a high impedance state. In this state, the clock line may float due to parasitic capacitive coupling and other effects caused by nearby signal paths in the component. The floating state of the clock line may, at times, resemble a clock transition. Such “false” transitions can trigger one or both of the components to latch unintended signals at their data ports. To prevent the floating state of the clock line from having these unintended effects, each component may include a clock filter to “isolate” the component from the clock line when the clock line is not being driven by a clock driver.
An example of a clock filter system 10 is shown in FIG. 1. Either one of two clock drivers, clock driverA 12 or clock driverB 14, generates a clock signal to (in this example) a bidirectional clock line (BICLOCK) 16 under the control of a memory controller (not shown). BICLOCK 16 includes buffers 32, 34 having outputs as inputs to AND gates 26, 28, respectively. In the illustrated example, each clock driver 12, 14 is associated with a component. Component A 18 has clock driverA 12 for generating clock signals when component A 18 is communicating data to component B 20. Similarly, component B has clock driverB 14 for generating clock signals when component B 20 is communicating data to component A 18. Component A 18 has a clock input 36 for receiving a clock signal (CLOCKB) from BICLOCK 16 when component B 20 is sending data. Similarly, component B 20 has a clock input 38 for receiving a clock signal (CLOCKA) from BICLOCK 16 when component A 18 is sending data.
D flip-flops 22 and 24 provide mask signals MASKA and MASKB to the AND gates 26 and 28, respectively. The mask signals are set low when BICLOCK 16 is not being driven, so that the AND gates 26 and 28 mask CLOCKB and CLOCKA from BICLOCK 16 when it is in a high impedance state. Stated another way, when BICLOCK 16 is floating, MASKA and MASKB are set low by control signals MASKN and MASKP, respectively, so that floating transitions cannot propagate through the AND gates 26, 28. The control signals MASKN and MASKP are usually provided by a memory controller.
When data is to be transmitted, for example from component A 18 to component B 20, along a data bus (not shown), clock driverA 12 generates a clock signal for component A 18 and for BICLOCK 16 for receipt at component B 20. A “preamble” defines the time interval starting when the clock driverA 12 initially drives BICLOCK (typically ↓) and ends just before the start of the first clock pulse. FIG. 2 is a timing diagram for transmitting a clock signal from clock driverA 12 to component B 20:                1.1 clock driverA and clock driverB are OFF; BICLOCK is in a high impedance state; MASKB is low to block CLOCKA from BICLOCK        1.2 clock driverA turns ON        1.3 Preamble: MASKP ↑ MASKB ↑        1.4 CLOCKA=BICLOCK (from clock driverA)        2.1 end of data transfer        2.2 MASKP ↓ MASKB ↓        2.3 clock driverA turns OFF; BICLOCK is again in a high impedance state        
At 2.2, MASKB will sample MASKP only when chip clock 30 goes high. Therefore, to ensure that MASKB masks CLOCKA from BICLOCK 16 at the correct time, chip clock 30 (inverted) must be aligned with BICLOCK 16. When the chip clock 30 and BICLOCK 16 are ideally aligned, MASKB goes low at C, the final set of data is latched at the right time, and CLOCKA is isolated from BICLOCK 16 at the right time. Stated another way, when MASKB goes low at C, the falling edge of CLOCKA is aligned with the falling edge of the last intended clock signal on BICLOCK 16. However, if chip clock 30 is not aligned to BICLOCK 16, MASKB (following MASKP) may go low too early E or too late L, as shown.
If MASKB goes low too early E, then CLOCKA will go low to early R, and component B 20 may latch in signals from the data bus before component A 18 has latched its data on the data bus. This may result in erroneous data being latched in component B 20.
Its possible that BICLOCK 16 may turn off (to a high impedance state) before CLOCKA is masked from BICLOCK 16. This would happen if MASKB goes low too late L. As stated above, in a high impedance state noise may be easily induced on BICLOCK 16. The noise may cause a glitch G on CLOCKA. The glitch G may cause component B 20 to latch in erroneous data from the data bus.
As stated earlier, accurate masking (C) is dependent upon having the chip clock 30 aligned with BICLOCK 16, i.e., with clock driverA 12 (and, in the opposite direction, with clock driverB 14). Meeting this timing constraint is difficult because clock driverA 12 and clock driverB 14 are inherently shifted in time from the chip clock 30 due to path delays on chip pads, board routing, and voltage, temperature, and process variations. Attempts to meet the timing constraint include adding circuitry to delay either the chip clock signal or the clock driver signals. However, adding circuitry results in further intricacies, increases costs, and adds another level of dependence on precise component specifications. An improved approach is desirable.